The present invention relates to a semiconductor device, a memory test method for a semiconductor device, and a test pattern generation program and, for example, relates to a semiconductor device having a memory BIST (Built-In Self-Test) function that performs a self test for an internal memory, a memory test method for the semiconductor device, and a test pattern generation program.
A semiconductor device including a memory has a function that detects a failure of the memory and performs a process of replacing a failure cell or a process of invalidating the failure cell to enable continuation of an operation as a system even when the failure occurs in the memory. To achieve this function, a semiconductor device including a memory incorporates a test circuit for testing the memory. An example of the semiconductor device including such a test circuit is disclosed in Japanese Unexamined Patent Application Publication No. 2012-234605.
The semiconductor device in Japanese Unexamined Patent Application Publication No. 2012-234605 includes a control circuit and first and second pattern generators. When both tests by the first and second test pattern generators are write, the control circuit permits execution of a test sequence by one of the test pattern generators and does not permit execution of a test sequence by the other test pattern generator, outputs a write test pattern from the one test pattern generator to a corresponding one of memory groups, shifts write execution for the other memory group in time by a unit of a write test cycle of the one memory group, permits execution of the test sequence by the other test pattern generator after writing for the one memory group by the one test pattern generator is finished, and outputs a write test pattern to the other memory group corresponding to the other test pattern generator.